錯誤1. 有解
Verilog HDL Procedural Assignment error at object on left-hand side of assignment must have a variable data type
以上代码有很明显的两点错误，不在quartus。
1，object "count_clr" on left-hand side of assignment must have a net type
这个意思是assign语句只能对wire型变量赋值。
2，Error (10137): Verilog HDL Procedural Assignment error at fre_ctr.v(6): object "count_en" on left-hand side of assignment must have a variable data type在always块语句里只能是reg型变量赋值。
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